/* Date Stamp: 8/23/2014 */

#ifndef IIO_MEMHP_h
#define IIO_MEMHP_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_MEMHP_DEV 5                                                            */
/* IIO_MEMHP_FUN 1                                                            */

/* VID_IIO_MEMHP_REG supported on:                                            */
/*       IVT_EP (0x20029000)                                                  */
/*       IVT_EX (0x20029000)                                                  */
/*       HSX (0x20029000)                                                     */
/*       BDX (0x20029000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_MEMHP_REG 0x09012000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_MEMHP_REG supported on:                                            */
/*       IVT_EP (0x20029002)                                                  */
/*       IVT_EX (0x20029002)                                                  */
/*       HSX (0x20029002)                                                     */
/*       BDX (0x20029002)                                                     */
/* Register default value on IVT_EP:    0x0E29                                */
/* Register default value on IVT_EX:    0x0E29                                */
/* Register default value on HSX:       0x2F29                                */
/* Register default value on BDX:       0x6F29                                */
#define DID_IIO_MEMHP_REG 0x09012002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100101001 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, LT)
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel Quick Path Interface
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
     */
  } Bits;
  UINT16 Data;
} DID_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x20029004)                                                  */
/*       IVT_EX (0x20029004)                                                  */
/*       HSX (0x20029004)                                                     */
/*       BDX (0x20029004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_MEMHP_REG 0x09012004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x004
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 10;
    /* rsvd_0 - Bits[9:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RW, default = 1'b0 
       1
     */
    UINT16 rsvd_11 : 5;
    /* rsvd_11 - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x20029006)                                                  */
/*       IVT_EX (0x20029006)                                                  */
/*       HSX (0x20029006)                                                     */
/*       BDX (0x20029006)                                                     */
/* Register default value:              0x0018                                */
#define PCISTS_IIO_MEMHP_REG 0x09012006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxstat : 1;
    /* intxstat - Bits[3:3], RO_V, default = 1'b1 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 rsvd_5 : 11;
    /* rsvd_5 - Bits[15:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_MEMHP_REG supported on:                                            */
/*       IVT_EP (0x10029008)                                                  */
/*       IVT_EX (0x10029008)                                                  */
/*       HSX (0x10029008)                                                     */
/*       BDX (0x10029008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_MEMHP_REG 0x09011008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x10029009)                                                  */
/*       IVT_EX (0x10029009)                                                  */
/*       HSX (0x10029009)                                                     */
/*       BDX (0x10029009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_MEMHP_REG 0x09011009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.1.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_MEMHP_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x2002900A)                                                  */
/*       IVT_EX (0x2002900A)                                                  */
/*       HSX (0x2002900A)                                                     */
/*       BDX (0x2002900A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_MEMHP_REG 0x0901200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x1002900C)                                                  */
/*       IVT_EX (0x1002900C)                                                  */
/*       HSX (0x1002900C)                                                     */
/*       BDX (0x1002900C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_MEMHP_REG 0x0901100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000 
       This register is set as RW for compatibility reasons only. Cacheline size for 
       processor is always 64B. 
     */
  } Bits;
  UINT8 Data;
} CLSR_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* PLAT_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x1002900D)                                                  */
/*       IVT_EX (0x1002900D)                                                  */
/*       HSX (0x1002900D)                                                     */
/*       BDX (0x1002900D)                                                     */
/* Register default value:              0x00                                  */
#define PLAT_IIO_MEMHP_REG 0x0901100D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x00d
 */
typedef union {
  struct {
    UINT8 primary_latency_timer : 8;
    /* primary_latency_timer - Bits[7:0], RO, default = 8'b00000000 
       Not applicable to PCI-Express. Hardwired to 00h.
     */
  } Bits;
  UINT8 Data;
} PLAT_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_MEMHP_REG supported on:                                            */
/*       IVT_EP (0x1002900E)                                                  */
/*       IVT_EX (0x1002900E)                                                  */
/*       HSX (0x1002900E)                                                     */
/*       BDX (0x1002900E)                                                     */
/* Register default value:              0x00                                  */
#define HDR_IIO_MEMHP_REG 0x0901100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b0 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* BIST_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x1002900F)                                                  */
/*       IVT_EX (0x1002900F)                                                  */
/*       HSX (0x1002900F)                                                     */
/*       BDX (0x1002900F)                                                     */
/* Register default value:              0x00                                  */
#define BIST_IIO_MEMHP_REG 0x0901100F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x00f
 */
typedef union {
  struct {
    UINT8 bist_tests : 8;
    /* bist_tests - Bits[7:0], RO, default = 8'b00000000 
       Not supported. Hardwired to 00h
     */
  } Bits;
  UINT8 Data;
} BIST_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x2002902C)                                                  */
/*       IVT_EX (0x2002902C)                                                  */
/*       HSX (0x2002902C)                                                     */
/*       BDX (0x2002902C)                                                     */
/* Register default value:              0x0000                                */
#define SVID_IIO_MEMHP_REG 0x0901202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SDID_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x2002902E)                                                  */
/*       IVT_EX (0x2002902E)                                                  */
/*       HSX (0x2002902E)                                                     */
/*       BDX (0x2002902E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_MEMHP_REG 0x0901202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x10029034)                                                  */
/*       IVT_EX (0x10029034)                                                  */
/*       HSX (0x10029034)                                                     */
/*       BDX (0x10029034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_MEMHP_REG 0x09011034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* INTL_IIO_MEMHP_REG supported on:                                           */
/*       IVT_EP (0x1002903C)                                                  */
/*       IVT_EX (0x1002903C)                                                  */
/*       HSX (0x1002903C)                                                     */
/*       BDX (0x1002903C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_MEMHP_REG 0x0901103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x1002903D)                                                  */
/*       IVT_EX (0x1002903D)                                                  */
/*       HSX (0x1002903D)                                                     */
/*       BDX (0x1002903D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_MEMHP_REG 0x0901103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MINGNT_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x1002903E)                                                  */
/*       IVT_EX (0x1002903E)                                                  */
/*       HSX (0x1002903E)                                                     */
/*       BDX (0x1002903E)                                                     */
/* Register default value:              0x00                                  */
#define MINGNT_IIO_MEMHP_REG 0x0901103E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x03e
 */
typedef union {
  struct {
    UINT8 mgv : 8;
    /* mgv - Bits[7:0], RO, default = 8'b00000000 
       The Device does not burst as a PCI compliant master.
     */
  } Bits;
  UINT8 Data;
} MINGNT_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MAXLAT_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x1002903F)                                                  */
/*       IVT_EX (0x1002903F)                                                  */
/*       HSX (0x1002903F)                                                     */
/*       BDX (0x1002903F)                                                     */
/* Register default value:              0x00                                  */
#define MAXLAT_IIO_MEMHP_REG 0x0901103F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x03f
 */
typedef union {
  struct {
    UINT8 mlv : 8;
    /* mlv - Bits[7:0], RO, default = 8'b00000000 
       The Device has no specific requirements for how often it needs to access the PCI 
       bus. 
     */
  } Bits;
  UINT8 Data;
} MAXLAT_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x40029040)                                                  */
/*       IVT_EX (0x40029040)                                                  */
/*       HSX (0x40029040)                                                     */
/*       BDX (0x40029040)                                                     */
/* Register default value:              0x00918010                            */
#define PXPCAP_IIO_MEMHP_REG 0x09014040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x040
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b10000000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0 
       N/A for integrated endpoints
     */
    UINT32 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[29:25], RO, default = 5'b00000 
       N/A for this device
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MSICAP_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x20029080)                                                  */
/*       IVT_EX (0x20029080)                                                  */
/*       HSX (0x20029080)                                                     */
/*       BDX (0x20029080)                                                     */
/* Register default value:              0x0005                                */
#define MSICAP_IIO_MEMHP_REG 0x09012080
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x080
 */
typedef union {
  struct {
    UINT16 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00000101  */
    UINT16 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b00000000  */
  } Bits;
  UINT16 Data;
} MSICAP_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MSICTL_IIO_MEMHP_REG supported on:                                         */
/*       IVT_EP (0x20029082)                                                  */
/*       IVT_EX (0x20029082)                                                  */
/*       HSX (0x20029082)                                                     */
/*       BDX (0x20029082)                                                     */
/* Register default value:              0x0080                                */
#define MSICTL_IIO_MEMHP_REG 0x09012082
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x082
 */
typedef union {
  struct {
    UINT16 msien : 1;
    /* msien - Bits[0:0], RW, default = 1'b0  */
    UINT16 mmc : 3;
    /* mmc - Bits[3:1], RO, default = 3'b000  */
    UINT16 mme : 3;
    /* mme - Bits[6:4], RO, default = 3'b000  */
    UINT16 b64ac : 1;
    /* b64ac - Bits[7:7], RO, default = 1'b1  */
    UINT16 pvmc : 1;
    /* pvmc - Bits[8:8], RO, default = 1'b0  */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} MSICTL_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MSIAR_IIO_MEMHP_REG supported on:                                          */
/*       IVT_EP (0x40029084)                                                  */
/*       IVT_EX (0x40029084)                                                  */
/*       HSX (0x40029084)                                                     */
/*       BDX (0x40029084)                                                     */
/* Register default value:              0x00000000                            */
#define MSIAR_IIO_MEMHP_REG 0x09014084
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * The MSI Address Register (MSIAR) contains the system specific address 
 * information to route MSI interrupts from the root ports and is broken into its 
 * constituent fields. 
 */
typedef union {
  struct {
    UINT32 mem_adr_const : 2;
    /* mem_adr_const - Bits[1:0], RO, default = 2'b00 
       1
     */
    UINT32 interrupt_address : 30;
    /* interrupt_address - Bits[31:2], RW, default = 30'b000000000000000000000000000000 
       1
     */
  } Bits;
  UINT32 Data;
} MSIAR_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MSIDR_IIO_MEMHP_REG supported on:                                          */
/*       IVT_EP (0x2002908C)                                                  */
/*       IVT_EX (0x2002908C)                                                  */
/*       HSX (0x2002908C)                                                     */
/*       BDX (0x2002908C)                                                     */
/* Register default value:              0x0000                                */
#define MSIDR_IIO_MEMHP_REG 0x0901208C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * generated by critter 05_1_0x08c
 */
typedef union {
  struct {
    UINT16 msidr_data : 16;
    /* msidr_data - Bits[15:0], RW, default = 16'b0000000000000000 
       1
     */
  } Bits;
  UINT16 Data;
} MSIDR_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPCTRL_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x400290A0)                                                  */
/*       IVT_EX (0x400290A0)                                                  */
/*       HSX (0x400290A0)                                                     */
/*       BDX (0x400290A0)                                                     */
/* Register default value:              0x00000000                            */
#define MEMHPCTRL_IIO_MEMHP_REG 0x090140A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Memory Hot Plug Control.
 */
typedef union {
  struct {
    UINT32 smien : 1;
    /* smien - Bits[0:0], RW, default = 1'b0 
       SMI Enable. Enable SMI interrupt generation on any hotplug event (regardless of 
       whether it is enabled in the MemHP capabilities). 
     */
    UINT32 hot_plug_event_status : 1;
    /* hot_plug_event_status - Bits[1:1], RO_V, default = 1'b0  */
    UINT32 enable_acpi_mode_for_hotplug : 1;
    /* enable_acpi_mode_for_hotplug - Bits[2:2], RW, default = 1'b0  */
    UINT32 rsvd : 29;
    /* rsvd - Bits[31:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MEMHPCTRL_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */




/* MEMHPCAP0_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029100)                                                  */
/*       IVT_EX (0x40029100)                                                  */
/*       HSX (0x40029100)                                                     */
/*       BDX (0x40029100)                                                     */
/* Register default value:              0x1101000B                            */
#define MEMHPCAP0_IIO_MEMHP_REG 0x09014100
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability 
 */
typedef union {
  struct {
    UINT32 vendor_specific_capability : 16;
    /* vendor_specific_capability - Bits[15:0], RO, default = 16'b0000000000001011  */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001  */
    UINT32 next_ptr : 12;
    /* next_ptr - Bits[31:20], RO, default = 12'b000100010000 
       Next Pointer. This points to the next capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPCAP0_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPHDR0_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029104)                                                  */
/*       IVT_EX (0x40029104)                                                  */
/*       HSX (0x40029104)                                                     */
/*       BDX (0x40029104)                                                     */
/* Register default value:              0x01010006                            */
#define MEMHPHDR0_IIO_MEMHP_REG 0x09014104
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability Header.
 */
typedef union {
  struct {
    UINT32 vendor_specific_id : 16;
    /* vendor_specific_id - Bits[15:0], RO, default = 16'b0000000000000110 
       Represents the Memory Hotplug Capability.
     */
    UINT32 vendor_specific_revision_id : 4;
    /* vendor_specific_revision_id - Bits[19:16], RO, default = 4'b0001 
       First revision of this capability structure.
     */
    UINT32 vendor_specific_length : 12;
    /* vendor_specific_length - Bits[31:20], RO, default = 12'b000000010000 
       There are 16 bytes in this capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPHDR0_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCAP0_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x40029108)                                                  */
/*       IVT_EX (0x40029108)                                                  */
/*       HSX (0x40029108)                                                     */
/*       BDX (0x40029108)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP0_IIO_MEMHP_REG 0x09014108
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Capability. 
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RW_O, default = 1'b0 
       This bit indicates that the Attention Button event signal is routed (from slot 
       or on-board in the chassis) to the IIOs hotplug controller. 
       0: indicates that an Attention Button signal is routed to IIO
       1: indicates that an Attention Button is not routed to IIO
       BIOS programs this field.
     */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RW_O, default = 1'b0 
       This bit indicates that a software controllable power controller is implemented 
       on the chassis for this slot. 
       0: indicates that a software controllable power controller is not present
       1: indicates that a software controllable power controller is present
       BIOS programs this field.
     */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RW_O, default = 1'b0 
       This bit indicates that an MRL Sensor is implemented on the chassis for this 
       slot. 
       0: indicates that an MRL Sensor is not present
       1: indicates that an MRL Sensor is present
       BIOS programs this field.
     */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RW_O, default = 1'b0 
       This bit indicates that an Attention Indicator is implemented for this slot and 
       is electrically controlled by the chassis 
       0: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is not present 
       1: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is present 
       BIOS programs this field.
     */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RW_O, default = 1'b0 
       This bit indicates that a Power Indicator is implemented for this slot and is 
       electrically controlled by the chassis. 
       0: indicates that a Power Indicator that is electrically controlled by the 
       chassis is not present. 
       1: indicates that Power Indicator that is electrically controlled by the chassis 
       is present. 
       BIOS programs this field.
     */
    UINT32 hot_plug_surprise : 1;
    /* hot_plug_surprise - Bits[5:5], RW_O, default = 1'b0 
       This field indicates that a device in this slot may be removed from the system 
       without prior notification. This field is initialized by BIOS. 
       0: indicates that hot-plug surprise is not supported.
       1: indicates that hot-plug surprise is supported.
       This bit is not set because there are no known usage models and no hardware 
       mechanism for detecting a surprise hotplug event. 
     */
    UINT32 hot_plug_capable : 1;
    /* hot_plug_capable - Bits[6:6], RW_O, default = 1'b0 
       This field defines hot-plug support capabilities for the Memory Channel.
       0: indicates that this slot is not capable of supporting Hot-plug operations.
       1: indicates that this slot is capable of supporting Hot-plug operations
       This bit is programmed by BIOS based on the system design. This bit must be 
       programmed by BIOS to be consistent with the VPP enable bit for the port. 
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[17:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0 
       If set, indicates that this structure is not capable of generating an interrupt 
       on completion of the last command. 
     */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RW_O, default = 13'b0000000000000 
       Indicates the associated memory channel number.
     */
  } Bits;
  UINT32 Data;
} SLTCAP0_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCON0_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002910C)                                                  */
/*       IVT_EX (0x2002910C)                                                  */
/*       HSX (0x2002910C)                                                     */
/*       BDX (0x2002910C)                                                     */
/* Register default value:              0x07C0                                */
#define SLTCON0_IIO_MEMHP_REG 0x0901210C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Control 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed_enable : 1;
    /* attention_button_pressed_enable - Bits[0:0], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via an 
       attention button pressed event. 
       0: Disables generation of hot-plug interrupts when the attention button is 
       pressed. 
       1: Enables generation of hot-plug interrupts when the attention button is 
       pressed. 
     */
    UINT16 power_fault_detected_enable : 1;
    /* power_fault_detected_enable - Bits[1:1], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       power fault event. 
       0: Disables generation of hot-plug interrupts when a power fault event happens.
       1: Enables generation of hot-plug interrupts when a power fault event happens.
     */
    UINT16 mrl_sensor_changed_enable : 1;
    /* mrl_sensor_changed_enable - Bits[2:2], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       MRL Sensor changed event. 
       0: Disables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
       1: Enables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
     */
    UINT16 presence_detect_changed_enable : 1;
    /* presence_detect_changed_enable - Bits[3:3], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       presence detect changed event. 
       0: Disables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
       1: Enables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
     */
    UINT16 command_completed_interrupt_enable : 1;
    /* command_completed_interrupt_enable - Bits[4:4], RW, default = 1'b0 
       This field enables software notification (Interrupt - MSI/INTx) when a command 
       is completed by the Hot-plug controller connected to the PCI Express port 
       0: Disables hot-plug interrupts on a command completion by a hot-plug Controller
       1: Enables hot-plug interrupts on a command completion by a hot-plug Controller
     */
    UINT16 hot_plug_interrupt_enable : 1;
    /* hot_plug_interrupt_enable - Bits[5:5], RW, default = 1'b0 
       When set to 1b, this bit enables generation of Hot-Plug interrupt, MSI or INTx 
       interrupt depending on the setting of the MSI enable bit in 'MSI Control 
       Register (MSICTRL)' on enabled Hot-Plug events. 
       0: Disables interrupt generation on Hot-plug events
       1: Enables interrupt generation on Hot-plug events
     */
    UINT16 attention_indicator_control : 2;
    /* attention_indicator_control - Bits[7:6], RW, default = 2'b11 
       If an Attention Indicator is implemented, writes to this field will set the 
       Attention Indicator to the written state. Reads of this field reflect the value 
       from the latest write, even if the corresponding hot-plug command is not 
       executed yet at the VPP, unless software issues a write without waiting for the 
       previous command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave)
       11: Off
     */
    UINT16 power_indicator_control : 2;
    /* power_indicator_control - Bits[9:8], RW, default = 2'b11 
       If a Power Indicator is implemented, writes to this field will set the Power 
       Indicator to the written state. Reads of this field must reflect the value from 
       the latest write, even if the corresponding hot-plug command is not executed yet 
       at the VPP, unless software issues a write without waiting for the previous 
       command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs)
       11: Off
     */
    UINT16 power_controller_control : 1;
    /* power_controller_control - Bits[10:10], RWS, default = 1'b1 
       If a power controller is implemented, when writes to this field will set the 
       power state of the slot as indicated by this bit. Reads of this field must 
       reflect the value from the latest write, even if the corresponding hot-plug 
       command is not executed yet at the VPP, unless software issues a write without 
       waiting for the previous command to complete in which case the read value is 
       undefined. 
       0: Power On
       1: Power Off
     */
    UINT16 electromechanical_interlock_control : 1;
    /* electromechanical_interlock_control - Bits[11:11], RW_V, default = 1'b0 
       When software writes a 1 to this bit, IIO pulses the EMIL pin. Write of 0 has no 
       effect. This bit always returns a 0 when read. If electromechanical lock is not 
       implemented, then either a write of 1 or 0 to this register has no effect. 
     */
    UINT16 rsvd : 4;
    /* rsvd - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTCON0_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTSTS0_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002910E)                                                  */
/*       IVT_EX (0x2002910E)                                                  */
/*       HSX (0x2002910E)                                                     */
/*       BDX (0x2002910E)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS0_IIO_MEMHP_REG 0x0901210E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Status. 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RW1C, default = 1'b0 
       This bit is set by IIO when the attention button is pressed. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RW1C, default = 1'b0 
       This bit is set by IIO when a power fault event is detected by the power 
       controller (which is reported via the VPP bit stream). It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RW1C, default = 1'b0 
       This bit is set if the value reported in bit 5 changes. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RW1C, default = 1'b0 
       This bit is set by IIO when the value reported in bit 6 is changes. It is 
       subsequently cleared by software after the field has been read and processed. 
     */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RW1C, default = 1'b0 
       This bit is set by IIO when the hot-plug command has completed and the hot-plug 
       controller is ready to accept a subsequent command. It is subsequently cleared 
       by software after the field has been read and processed. This bit provides no 
       guarantee that the action corresponding to the command is complete. 
       Any write to SLTCON (regardless of the port is capable or enabled for hot-plug) 
       is considered a 'hot-plug' command. If the port is not hot-plug capable or 
       hot-plug enabled, then the hot-plug command does not trigger any action on the 
       VPP port but the command is still completed via this bit. 
     */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO_V, default = 1'b0 
       This bit reports the status of an MRL sensor if it is implemented.
       0: MRL Closed
       1: MRL Open
     */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO_V, default = 1'b0 
       When read, this register returns the current state of the Present Detect pin.
       0: Module slot empty
       1: Module Present in slot (powered or unpowered)
     */
    UINT16 rsvd : 9;
    /* rsvd - Bits[15:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS0_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPCAP1_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029110)                                                  */
/*       IVT_EX (0x40029110)                                                  */
/*       HSX (0x40029110)                                                     */
/*       BDX (0x40029110)                                                     */
/* Register default value:              0x1201000B                            */
#define MEMHPCAP1_IIO_MEMHP_REG 0x09014110
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability 
 */
typedef union {
  struct {
    UINT32 vendor_specific_capability : 16;
    /* vendor_specific_capability - Bits[15:0], RO, default = 16'b0000000000001011  */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001  */
    UINT32 next_ptr : 12;
    /* next_ptr - Bits[31:20], RO, default = 12'b000100100000 
       Next Pointer. This points to the next capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPCAP1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPHDR1_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029114)                                                  */
/*       IVT_EX (0x40029114)                                                  */
/*       HSX (0x40029114)                                                     */
/*       BDX (0x40029114)                                                     */
/* Register default value:              0x01010006                            */
#define MEMHPHDR1_IIO_MEMHP_REG 0x09014114
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability Header.
 */
typedef union {
  struct {
    UINT32 vendor_specific_id : 16;
    /* vendor_specific_id - Bits[15:0], RO, default = 16'b0000000000000110 
       Represents the Memory Hotplug Capability.
     */
    UINT32 vendor_specific_revision_id : 4;
    /* vendor_specific_revision_id - Bits[19:16], RO, default = 4'b0001 
       First revision of this capability structure.
     */
    UINT32 vendor_specific_length : 12;
    /* vendor_specific_length - Bits[31:20], RO, default = 12'b000000010000 
       There are 16 bytes in this capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPHDR1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCAP1_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x40029118)                                                  */
/*       IVT_EX (0x40029118)                                                  */
/*       HSX (0x40029118)                                                     */
/*       BDX (0x40029118)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP1_IIO_MEMHP_REG 0x09014118
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Capability. 
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RW_O, default = 1'b0 
       This bit indicates that the Attention Button event signal is routed (from slot 
       or on-board in the chassis) to the IIOs hotplug controller. 
       0: indicates that an Attention Button signal is routed to IIO
       1: indicates that an Attention Button is not routed to IIO
       BIOS programs this field.
     */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RW_O, default = 1'b0 
       This bit indicates that a software controllable power controller is implemented 
       on the chassis for this slot. 
       0: indicates that a software controllable power controller is not present
       1: indicates that a software controllable power controller is present
       BIOS programs this field.
     */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RW_O, default = 1'b0 
       This bit indicates that an MRL Sensor is implemented on the chassis for this 
       slot. 
       0: indicates that an MRL Sensor is not present
       1: indicates that an MRL Sensor is present
       BIOS programs this field.
     */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RW_O, default = 1'b0 
       This bit indicates that an Attention Indicator is implemented for this slot and 
       is electrically controlled by the chassis 
       0: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is not present 
       1: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is present 
       BIOS programs this field.
     */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RW_O, default = 1'b0 
       This bit indicates that a Power Indicator is implemented for this slot and is 
       electrically controlled by the chassis. 
       0: indicates that a Power Indicator that is electrically controlled by the 
       chassis is not present. 
       1: indicates that Power Indicator that is electrically controlled by the chassis 
       is present. 
       BIOS programs this field.
     */
    UINT32 hot_plug_surprise : 1;
    /* hot_plug_surprise - Bits[5:5], RW_O, default = 1'b0 
       This field indicates that a device in this slot may be removed from the system 
       without prior notification. This field is initialized by BIOS. 
       0: indicates that hot-plug surprise is not supported.
       1: indicates that hot-plug surprise is supported.
       This bit is not set because there are no known usage models and no hardware 
       mechanism for detecting a surprise hotplug event. 
     */
    UINT32 hot_plug_capable : 1;
    /* hot_plug_capable - Bits[6:6], RW_O, default = 1'b0 
       This field defines hot-plug support capabilities for the Memory Channel.
       0: indicates that this slot is not capable of supporting Hot-plug operations.
       1: indicates that this slot is capable of supporting Hot-plug operations
       This bit is programmed by BIOS based on the system design. This bit must be 
       programmed by BIOS to be consistent with the VPP enable bit for the port. 
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[17:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0 
       If set, indicates that this structure is not capable of generating an interrupt 
       on completion of the last command. 
     */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RW_O, default = 13'b0000000000000 
       Indicates the associated memory channel number.
     */
  } Bits;
  UINT32 Data;
} SLTCAP1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCON1_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002911C)                                                  */
/*       IVT_EX (0x2002911C)                                                  */
/*       HSX (0x2002911C)                                                     */
/*       BDX (0x2002911C)                                                     */
/* Register default value:              0x07C0                                */
#define SLTCON1_IIO_MEMHP_REG 0x0901211C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Control 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed_enable : 1;
    /* attention_button_pressed_enable - Bits[0:0], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via an 
       attention button pressed event. 
       0: Disables generation of hot-plug interrupts when the attention button is 
       pressed. 
       1: Enables generation of hot-plug interrupts when the attention button is 
       pressed. 
     */
    UINT16 power_fault_detected_enable : 1;
    /* power_fault_detected_enable - Bits[1:1], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       power fault event. 
       0: Disables generation of hot-plug interrupts when a power fault event happens.
       1: Enables generation of hot-plug interrupts when a power fault event happens.
     */
    UINT16 mrl_sensor_changed_enable : 1;
    /* mrl_sensor_changed_enable - Bits[2:2], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       MRL Sensor changed event. 
       0: Disables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
       1: Enables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
     */
    UINT16 presence_detect_changed_enable : 1;
    /* presence_detect_changed_enable - Bits[3:3], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       presence detect changed event. 
       0: Disables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
       1: Enables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
     */
    UINT16 command_completed_interrupt_enable : 1;
    /* command_completed_interrupt_enable - Bits[4:4], RW, default = 1'b0 
       This field enables software notification (Interrupt - MSI/INTx) when a command 
       is completed by the Hot-plug controller connected to the PCI Express port 
       0: Disables hot-plug interrupts on a command completion by a hot-plug Controller
       1: Enables hot-plug interrupts on a command completion by a hot-plug Controller
     */
    UINT16 hot_plug_interrupt_enable : 1;
    /* hot_plug_interrupt_enable - Bits[5:5], RW, default = 1'b0 
       When set to 1b, this bit enables generation of Hot-Plug interrupt, MSI or INTx 
       interrupt depending on the setting of the MSI enable bit in 'MSI Control 
       Register (MSICTRL)' on enabled Hot-Plug events. 
       0: Disables interrupt generation on Hot-plug events
       1: Enables interrupt generation on Hot-plug events
     */
    UINT16 attention_indicator_control : 2;
    /* attention_indicator_control - Bits[7:6], RW, default = 2'b11 
       If an Attention Indicator is implemented, writes to this field will set the 
       Attention Indicator to the written state. Reads of this field reflect the value 
       from the latest write, even if the corresponding hot-plug command is not 
       executed yet at the VPP, unless software issues a write without waiting for the 
       previous command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave)
       11: Off
     */
    UINT16 power_indicator_control : 2;
    /* power_indicator_control - Bits[9:8], RW, default = 2'b11 
       If a Power Indicator is implemented, writes to this field will set the Power 
       Indicator to the written state. Reads of this field must reflect the value from 
       the latest write, even if the corresponding hot-plug command is not executed yet 
       at the VPP, unless software issues a write without waiting for the previous 
       command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs)
       11: Off
     */
    UINT16 power_controller_control : 1;
    /* power_controller_control - Bits[10:10], RWS, default = 1'b1 
       If a power controller is implemented, when writes to this field will set the 
       power state of the slot as indicated by this bit. Reads of this field must 
       reflect the value from the latest write, even if the corresponding hot-plug 
       command is not executed yet at the VPP, unless software issues a write without 
       waiting for the previous command to complete in which case the read value is 
       undefined. 
       0: Power On
       1: Power Off
     */
    UINT16 electromechanical_interlock_control : 1;
    /* electromechanical_interlock_control - Bits[11:11], RW_V, default = 1'b0 
       When software writes a 1 to this bit, IIO pulses the EMIL pin. Write of 0 has no 
       effect. This bit always returns a 0 when read. If electromechanical lock is not 
       implemented, then either a write of 1 or 0 to this register has no effect. 
     */
    UINT16 rsvd : 4;
    /* rsvd - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTCON1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTSTS1_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002911E)                                                  */
/*       IVT_EX (0x2002911E)                                                  */
/*       HSX (0x2002911E)                                                     */
/*       BDX (0x2002911E)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS1_IIO_MEMHP_REG 0x0901211E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Status. 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RW1C, default = 1'b0 
       This bit is set by IIO when the attention button is pressed. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RW1C, default = 1'b0 
       This bit is set by IIO when a power fault event is detected by the power 
       controller (which is reported via the VPP bit stream). It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RW1C, default = 1'b0 
       This bit is set if the value reported in bit 5 changes. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RW1C, default = 1'b0 
       This bit is set by IIO when the value reported in bit 6 is changes. It is 
       subsequently cleared by software after the field has been read and processed. 
     */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RW1C, default = 1'b0 
       This bit is set by IIO when the hot-plug command has completed and the hot-plug 
       controller is ready to accept a subsequent command. It is subsequently cleared 
       by software after the field has been read and processed. This bit provides no 
       guarantee that the action corresponding to the command is complete. 
       Any write to SLTCON (regardless of the port is capable or enabled for hot-plug) 
       is considered a 'hot-plug' command. If the port is not hot-plug capable or 
       hot-plug enabled, then the hot-plug command does not trigger any action on the 
       VPP port but the command is still completed via this bit. 
     */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO_V, default = 1'b0 
       This bit reports the status of an MRL sensor if it is implemented.
       0: MRL Closed
       1: MRL Open
     */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO_V, default = 1'b0 
       When read, this register returns the current state of the Present Detect pin.
       0: Module slot empty
       1: Module Present in slot (powered or unpowered)
     */
    UINT16 rsvd : 9;
    /* rsvd - Bits[15:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS1_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPCAP2_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029120)                                                  */
/*       IVT_EX (0x40029120)                                                  */
/*       HSX (0x40029120)                                                     */
/*       BDX (0x40029120)                                                     */
/* Register default value:              0x1301000B                            */
#define MEMHPCAP2_IIO_MEMHP_REG 0x09014120
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability 
 */
typedef union {
  struct {
    UINT32 vendor_specific_capability : 16;
    /* vendor_specific_capability - Bits[15:0], RO, default = 16'b0000000000001011  */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001  */
    UINT32 next_ptr : 12;
    /* next_ptr - Bits[31:20], RO, default = 12'b000100110000 
       Next Pointer. This points to the next capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPCAP2_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPHDR2_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029124)                                                  */
/*       IVT_EX (0x40029124)                                                  */
/*       HSX (0x40029124)                                                     */
/*       BDX (0x40029124)                                                     */
/* Register default value:              0x01010006                            */
#define MEMHPHDR2_IIO_MEMHP_REG 0x09014124
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability Header.
 */
typedef union {
  struct {
    UINT32 vendor_specific_id : 16;
    /* vendor_specific_id - Bits[15:0], RO, default = 16'b0000000000000110 
       Represents the Memory Hotplug Capability.
     */
    UINT32 vendor_specific_revision_id : 4;
    /* vendor_specific_revision_id - Bits[19:16], RO, default = 4'b0001 
       First revision of this capability structure.
     */
    UINT32 vendor_specific_length : 12;
    /* vendor_specific_length - Bits[31:20], RO, default = 12'b000000010000 
       There are 16 bytes in this capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPHDR2_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCAP2_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x40029128)                                                  */
/*       IVT_EX (0x40029128)                                                  */
/*       HSX (0x40029128)                                                     */
/*       BDX (0x40029128)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP2_IIO_MEMHP_REG 0x09014128
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Capability. 
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RW_O, default = 1'b0 
       This bit indicates that the Attention Button event signal is routed (from slot 
       or on-board in the chassis) to the IIOs hotplug controller. 
       0: indicates that an Attention Button signal is routed to IIO
       1: indicates that an Attention Button is not routed to IIO
       BIOS programs this field.
     */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RW_O, default = 1'b0 
       This bit indicates that a software controllable power controller is implemented 
       on the chassis for this slot. 
       0: indicates that a software controllable power controller is not present
       1: indicates that a software controllable power controller is present
       BIOS programs this field.
     */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RW_O, default = 1'b0 
       This bit indicates that an MRL Sensor is implemented on the chassis for this 
       slot. 
       0: indicates that an MRL Sensor is not present
       1: indicates that an MRL Sensor is present
       BIOS programs this field.
     */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RW_O, default = 1'b0 
       This bit indicates that an Attention Indicator is implemented for this slot and 
       is electrically controlled by the chassis 
       0: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is not present 
       1: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is present 
       BIOS programs this field.
     */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RW_O, default = 1'b0 
       This bit indicates that a Power Indicator is implemented for this slot and is 
       electrically controlled by the chassis. 
       0: indicates that a Power Indicator that is electrically controlled by the 
       chassis is not present. 
       1: indicates that Power Indicator that is electrically controlled by the chassis 
       is present. 
       BIOS programs this field.
     */
    UINT32 hot_plug_surprise : 1;
    /* hot_plug_surprise - Bits[5:5], RW_O, default = 1'b0 
       This field indicates that a device in this slot may be removed from the system 
       without prior notification. This field is initialized by BIOS. 
       0: indicates that hot-plug surprise is not supported.
       1: indicates that hot-plug surprise is supported.
       This bit is not set because there are no known usage models and no hardware 
       mechanism for detecting a surprise hotplug event. 
     */
    UINT32 hot_plug_capable : 1;
    /* hot_plug_capable - Bits[6:6], RW_O, default = 1'b0 
       This field defines hot-plug support capabilities for the Memory Channel.
       0: indicates that this slot is not capable of supporting Hot-plug operations.
       1: indicates that this slot is capable of supporting Hot-plug operations
       This bit is programmed by BIOS based on the system design. This bit must be 
       programmed by BIOS to be consistent with the VPP enable bit for the port. 
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[17:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0 
       If set, indicates that this structure is not capable of generating an interrupt 
       on completion of the last command. 
     */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RW_O, default = 13'b0000000000000 
       Indicates the associated memory channel number.
     */
  } Bits;
  UINT32 Data;
} SLTCAP2_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCON2_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002912C)                                                  */
/*       IVT_EX (0x2002912C)                                                  */
/*       HSX (0x2002912C)                                                     */
/*       BDX (0x2002912C)                                                     */
/* Register default value:              0x07C0                                */
#define SLTCON2_IIO_MEMHP_REG 0x0901212C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Control 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed_enable : 1;
    /* attention_button_pressed_enable - Bits[0:0], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via an 
       attention button pressed event. 
       0: Disables generation of hot-plug interrupts when the attention button is 
       pressed. 
       1: Enables generation of hot-plug interrupts when the attention button is 
       pressed. 
     */
    UINT16 power_fault_detected_enable : 1;
    /* power_fault_detected_enable - Bits[1:1], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       power fault event. 
       0: Disables generation of hot-plug interrupts when a power fault event happens.
       1: Enables generation of hot-plug interrupts when a power fault event happens.
     */
    UINT16 mrl_sensor_changed_enable : 1;
    /* mrl_sensor_changed_enable - Bits[2:2], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       MRL Sensor changed event. 
       0: Disables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
       1: Enables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
     */
    UINT16 presence_detect_changed_enable : 1;
    /* presence_detect_changed_enable - Bits[3:3], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       presence detect changed event. 
       0: Disables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
       1: Enables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
     */
    UINT16 command_completed_interrupt_enable : 1;
    /* command_completed_interrupt_enable - Bits[4:4], RW, default = 1'b0 
       This field enables software notification (Interrupt - MSI/INTx) when a command 
       is completed by the Hot-plug controller connected to the PCI Express port 
       0: Disables hot-plug interrupts on a command completion by a hot-plug Controller
       1: Enables hot-plug interrupts on a command completion by a hot-plug Controller
     */
    UINT16 hot_plug_interrupt_enable : 1;
    /* hot_plug_interrupt_enable - Bits[5:5], RW, default = 1'b0 
       When set to 1b, this bit enables generation of Hot-Plug interrupt, MSI or INTx 
       interrupt depending on the setting of the MSI enable bit in 'MSI Control 
       Register (MSICTRL)' on enabled Hot-Plug events. 
       0: Disables interrupt generation on Hot-plug events
       1: Enables interrupt generation on Hot-plug events
     */
    UINT16 attention_indicator_control : 2;
    /* attention_indicator_control - Bits[7:6], RW, default = 2'b11 
       If an Attention Indicator is implemented, writes to this field will set the 
       Attention Indicator to the written state. Reads of this field reflect the value 
       from the latest write, even if the corresponding hot-plug command is not 
       executed yet at the VPP, unless software issues a write without waiting for the 
       previous command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave)
       11: Off
     */
    UINT16 power_indicator_control : 2;
    /* power_indicator_control - Bits[9:8], RW, default = 2'b11 
       If a Power Indicator is implemented, writes to this field will set the Power 
       Indicator to the written state. Reads of this field must reflect the value from 
       the latest write, even if the corresponding hot-plug command is not executed yet 
       at the VPP, unless software issues a write without waiting for the previous 
       command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs)
       11: Off
     */
    UINT16 power_controller_control : 1;
    /* power_controller_control - Bits[10:10], RWS, default = 1'b1 
       If a power controller is implemented, when writes to this field will set the 
       power state of the slot as indicated by this bit. Reads of this field must 
       reflect the value from the latest write, even if the corresponding hot-plug 
       command is not executed yet at the VPP, unless software issues a write without 
       waiting for the previous command to complete in which case the read value is 
       undefined. 
       0: Power On
       1: Power Off
     */
    UINT16 electromechanical_interlock_control : 1;
    /* electromechanical_interlock_control - Bits[11:11], RW_V, default = 1'b0 
       When software writes a 1 to this bit, IIO pulses the EMIL pin. Write of 0 has no 
       effect. This bit always returns a 0 when read. If electromechanical lock is not 
       implemented, then either a write of 1 or 0 to this register has no effect. 
     */
    UINT16 rsvd : 4;
    /* rsvd - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTCON2_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTSTS2_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002912E)                                                  */
/*       IVT_EX (0x2002912E)                                                  */
/*       HSX (0x2002912E)                                                     */
/*       BDX (0x2002912E)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS2_IIO_MEMHP_REG 0x0901212E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Status. 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RW1C, default = 1'b0 
       This bit is set by IIO when the attention button is pressed. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RW1C, default = 1'b0 
       This bit is set by IIO when a power fault event is detected by the power 
       controller (which is reported via the VPP bit stream). It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RW1C, default = 1'b0 
       This bit is set if the value reported in bit 5 changes. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RW1C, default = 1'b0 
       This bit is set by IIO when the value reported in bit 6 is changes. It is 
       subsequently cleared by software after the field has been read and processed. 
     */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RW1C, default = 1'b0 
       This bit is set by IIO when the hot-plug command has completed and the hot-plug 
       controller is ready to accept a subsequent command. It is subsequently cleared 
       by software after the field has been read and processed. This bit provides no 
       guarantee that the action corresponding to the command is complete. 
       Any write to SLTCON (regardless of the port is capable or enabled for hot-plug) 
       is considered a 'hot-plug' command. If the port is not hot-plug capable or 
       hot-plug enabled, then the hot-plug command does not trigger any action on the 
       VPP port but the command is still completed via this bit. 
     */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO_V, default = 1'b0 
       This bit reports the status of an MRL sensor if it is implemented.
       0: MRL Closed
       1: MRL Open
     */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO_V, default = 1'b0 
       When read, this register returns the current state of the Present Detect pin.
       0: Module slot empty
       1: Module Present in slot (powered or unpowered)
     */
    UINT16 rsvd : 9;
    /* rsvd - Bits[15:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS2_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPCAP3_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029130)                                                  */
/*       IVT_EX (0x40029130)                                                  */
/*       HSX (0x40029130)                                                     */
/*       BDX (0x40029130)                                                     */
/* Register default value:              0x0001000B                            */
#define MEMHPCAP3_IIO_MEMHP_REG 0x09014130
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability 
 */
typedef union {
  struct {
    UINT32 vendor_specific_capability : 16;
    /* vendor_specific_capability - Bits[15:0], RO, default = 16'b0000000000001011  */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001  */
    UINT32 next_ptr : 12;
    /* next_ptr - Bits[31:20], RO, default = 12'b000000000000 
       Next Pointer. This points to the next capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPCAP3_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* MEMHPHDR3_IIO_MEMHP_REG supported on:                                      */
/*       IVT_EP (0x40029134)                                                  */
/*       IVT_EX (0x40029134)                                                  */
/*       HSX (0x40029134)                                                     */
/*       BDX (0x40029134)                                                     */
/* Register default value:              0x01010006                            */
#define MEMHPHDR3_IIO_MEMHP_REG 0x09014134
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Memory Hot Plug Capability Header.
 */
typedef union {
  struct {
    UINT32 vendor_specific_id : 16;
    /* vendor_specific_id - Bits[15:0], RO, default = 16'b0000000000000110 
       Represents the Memory Hotplug Capability.
     */
    UINT32 vendor_specific_revision_id : 4;
    /* vendor_specific_revision_id - Bits[19:16], RO, default = 4'b0001 
       First revision of this capability structure.
     */
    UINT32 vendor_specific_length : 12;
    /* vendor_specific_length - Bits[31:20], RO, default = 12'b000000010000 
       There are 16 bytes in this capability structure.
     */
  } Bits;
  UINT32 Data;
} MEMHPHDR3_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCAP3_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x40029138)                                                  */
/*       IVT_EX (0x40029138)                                                  */
/*       HSX (0x40029138)                                                     */
/*       BDX (0x40029138)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP3_IIO_MEMHP_REG 0x09014138
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Capability. 
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RW_O, default = 1'b0 
       This bit indicates that the Attention Button event signal is routed (from slot 
       or on-board in the chassis) to the IIOs hotplug controller. 
       0: indicates that an Attention Button signal is routed to IIO
       1: indicates that an Attention Button is not routed to IIO
       BIOS programs this field.
     */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RW_O, default = 1'b0 
       This bit indicates that a software controllable power controller is implemented 
       on the chassis for this slot. 
       0: indicates that a software controllable power controller is not present
       1: indicates that a software controllable power controller is present
       BIOS programs this field.
     */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RW_O, default = 1'b0 
       This bit indicates that an MRL Sensor is implemented on the chassis for this 
       slot. 
       0: indicates that an MRL Sensor is not present
       1: indicates that an MRL Sensor is present
       BIOS programs this field.
     */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RW_O, default = 1'b0 
       This bit indicates that an Attention Indicator is implemented for this slot and 
       is electrically controlled by the chassis 
       0: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is not present 
       1: indicates that an Attention Indicator that is electrically controlled by the 
       chassis is present 
       BIOS programs this field.
     */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RW_O, default = 1'b0 
       This bit indicates that a Power Indicator is implemented for this slot and is 
       electrically controlled by the chassis. 
       0: indicates that a Power Indicator that is electrically controlled by the 
       chassis is not present. 
       1: indicates that Power Indicator that is electrically controlled by the chassis 
       is present. 
       BIOS programs this field.
     */
    UINT32 hot_plug_surprise : 1;
    /* hot_plug_surprise - Bits[5:5], RW_O, default = 1'b0 
       This field indicates that a device in this slot may be removed from the system 
       without prior notification. This field is initialized by BIOS. 
       0: indicates that hot-plug surprise is not supported.
       1: indicates that hot-plug surprise is supported.
       This bit is not set because there are no known usage models and no hardware 
       mechanism for detecting a surprise hotplug event. 
     */
    UINT32 hot_plug_capable : 1;
    /* hot_plug_capable - Bits[6:6], RW_O, default = 1'b0 
       This field defines hot-plug support capabilities for the Memory Channel.
       0: indicates that this slot is not capable of supporting Hot-plug operations.
       1: indicates that this slot is capable of supporting Hot-plug operations
       This bit is programmed by BIOS based on the system design. This bit must be 
       programmed by BIOS to be consistent with the VPP enable bit for the port. 
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[17:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0 
       If set, indicates that this structure is not capable of generating an interrupt 
       on completion of the last command. 
     */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RW_O, default = 13'b0000000000000 
       Indicates the associated memory channel number.
     */
  } Bits;
  UINT32 Data;
} SLTCAP3_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTCON3_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002913C)                                                  */
/*       IVT_EX (0x2002913C)                                                  */
/*       HSX (0x2002913C)                                                     */
/*       BDX (0x2002913C)                                                     */
/* Register default value:              0x07C0                                */
#define SLTCON3_IIO_MEMHP_REG 0x0901213C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Control 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed_enable : 1;
    /* attention_button_pressed_enable - Bits[0:0], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via an 
       attention button pressed event. 
       0: Disables generation of hot-plug interrupts when the attention button is 
       pressed. 
       1: Enables generation of hot-plug interrupts when the attention button is 
       pressed. 
     */
    UINT16 power_fault_detected_enable : 1;
    /* power_fault_detected_enable - Bits[1:1], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       power fault event. 
       0: Disables generation of hot-plug interrupts when a power fault event happens.
       1: Enables generation of hot-plug interrupts when a power fault event happens.
     */
    UINT16 mrl_sensor_changed_enable : 1;
    /* mrl_sensor_changed_enable - Bits[2:2], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       MRL Sensor changed event. 
       0: Disables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
       1: Enables generation of hot-plug interrupts when an MRL Sensor changed event 
       happens. 
     */
    UINT16 presence_detect_changed_enable : 1;
    /* presence_detect_changed_enable - Bits[3:3], RW, default = 1'b0 
       This bit enables the generation of hot-plug interrupts or wake messages via a 
       presence detect changed event. 
       0: Disables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
       1: Enables generation of hot-plug interrupts when a presence detect changed 
       event happens. 
     */
    UINT16 command_completed_interrupt_enable : 1;
    /* command_completed_interrupt_enable - Bits[4:4], RW, default = 1'b0 
       This field enables software notification (Interrupt - MSI/INTx) when a command 
       is completed by the Hot-plug controller connected to the PCI Express port 
       0: Disables hot-plug interrupts on a command completion by a hot-plug Controller
       1: Enables hot-plug interrupts on a command completion by a hot-plug Controller
     */
    UINT16 hot_plug_interrupt_enable : 1;
    /* hot_plug_interrupt_enable - Bits[5:5], RW, default = 1'b0 
       When set to 1b, this bit enables generation of Hot-Plug interrupt, MSI or INTx 
       interrupt depending on the setting of the MSI enable bit in 'MSI Control 
       Register (MSICTRL)' on enabled Hot-Plug events. 
       0: Disables interrupt generation on Hot-plug events
       1: Enables interrupt generation on Hot-plug events
     */
    UINT16 attention_indicator_control : 2;
    /* attention_indicator_control - Bits[7:6], RW, default = 2'b11 
       If an Attention Indicator is implemented, writes to this field will set the 
       Attention Indicator to the written state. Reads of this field reflect the value 
       from the latest write, even if the corresponding hot-plug command is not 
       executed yet at the VPP, unless software issues a write without waiting for the 
       previous command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave)
       11: Off
     */
    UINT16 power_indicator_control : 2;
    /* power_indicator_control - Bits[9:8], RW, default = 2'b11 
       If a Power Indicator is implemented, writes to this field will set the Power 
       Indicator to the written state. Reads of this field must reflect the value from 
       the latest write, even if the corresponding hot-plug command is not executed yet 
       at the VPP, unless software issues a write without waiting for the previous 
       command to complete in which case the read value is undefined. 
       00: Reserved
       01: On
       10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs)
       11: Off
     */
    UINT16 power_controller_control : 1;
    /* power_controller_control - Bits[10:10], RWS, default = 1'b1 
       If a power controller is implemented, when writes to this field will set the 
       power state of the slot as indicated by this bit. Reads of this field must 
       reflect the value from the latest write, even if the corresponding hot-plug 
       command is not executed yet at the VPP, unless software issues a write without 
       waiting for the previous command to complete in which case the read value is 
       undefined. 
       0: Power On
       1: Power Off
     */
    UINT16 electromechanical_interlock_control : 1;
    /* electromechanical_interlock_control - Bits[11:11], RW_V, default = 1'b0 
       When software writes a 1 to this bit, IIO pulses the EMIL pin. Write of 0 has no 
       effect. This bit always returns a 0 when read. If electromechanical lock is not 
       implemented, then either a write of 1 or 0 to this register has no effect. 
     */
    UINT16 rsvd : 4;
    /* rsvd - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTCON3_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


/* SLTSTS3_IIO_MEMHP_REG supported on:                                        */
/*       IVT_EP (0x2002913E)                                                  */
/*       IVT_EX (0x2002913E)                                                  */
/*       HSX (0x2002913E)                                                     */
/*       BDX (0x2002913E)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS3_IIO_MEMHP_REG 0x0901213E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.1.CFG.xml.
 * Channel X Slot Status. 
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RW1C, default = 1'b0 
       This bit is set by IIO when the attention button is pressed. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RW1C, default = 1'b0 
       This bit is set by IIO when a power fault event is detected by the power 
       controller (which is reported via the VPP bit stream). It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RW1C, default = 1'b0 
       This bit is set if the value reported in bit 5 changes. It is subsequently 
       cleared by software after the field has been read and processed. 
     */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RW1C, default = 1'b0 
       This bit is set by IIO when the value reported in bit 6 is changes. It is 
       subsequently cleared by software after the field has been read and processed. 
     */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RW1C, default = 1'b0 
       This bit is set by IIO when the hot-plug command has completed and the hot-plug 
       controller is ready to accept a subsequent command. It is subsequently cleared 
       by software after the field has been read and processed. This bit provides no 
       guarantee that the action corresponding to the command is complete. 
       Any write to SLTCON (regardless of the port is capable or enabled for hot-plug) 
       is considered a 'hot-plug' command. If the port is not hot-plug capable or 
       hot-plug enabled, then the hot-plug command does not trigger any action on the 
       VPP port but the command is still completed via this bit. 
     */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO_V, default = 1'b0 
       This bit reports the status of an MRL sensor if it is implemented.
       0: MRL Closed
       1: MRL Open
     */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO_V, default = 1'b0 
       When read, this register returns the current state of the Present Detect pin.
       0: Module slot empty
       1: Module Present in slot (powered or unpowered)
     */
    UINT16 rsvd : 9;
    /* rsvd - Bits[15:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS3_IIO_MEMHP_STRUCT;
#endif /* ASM_INC */


#endif /* IIO_MEMHP_h */
